1. Field of the Invention
The present invention relates to improvements in semiconductor circuits and MOS-DRAMs, which use fabricated from MOS-FETs.
2. Description of Related Art
FIG. 1 is a circuit diagram showing a complementary MOS inverter used in a conventional semiconductor circuit. Power source potential V.sub.CC is applied to the source and backgate (substrate) of a pMOS-FET Q1, and ground potential V.sub.SS is applied to the source and backgate of an nMOS-FET Q2. The gates of the FETs Q1 and Q2 are connected to form an input node IN, and their drains are connected to form an output node OUT.
The operation of the thus configured complementary MOS inverter will be described below.
When a logic signal of high level (power source potential V.sub.CC) is inputted to the input node IN, the FET Q1 is turned off and the FET Q2 is turned on, so that a logic signal of low level (ground potential V.sub.SS =0 V) is outputted from the output node OUT through the FET Q2.
Conversely, when a logic signal of low level (ground potential V.sub.SS =0 V) is inputted from the input node IN, the FET Q1 is turned on and the FET Q2 is turned off, so that a logic signal of high level (power source potential V.sub.CC) is outputted from the output node OUT through the FET Q1.
With increasing miniaturization of semiconductor circuits and scaling-down of individual MOS-FETs used in semiconductor circuits, MOS-FET performance has been increasing. More specifically, by making the channel length shorter and by reducing the gate oxide thickness and thereby reducing the magnitude of the threshold voltage, higher switching speeds are achieved.
When the threshold voltage is reduced or the channel length is made shorter for MOS-FETs to achieve higher switching speeds, there arises the problem that the drain and source depletion layers can easily be connected together, causing a punch-through situation where current flows between source and drain even when the channel is not formed. This increases the subthreshold current that flows under weak inversion when the gate voltage is near and below the threshold voltage.
FIG. 2 is a cross-sectional view schematically showing a conventional memory cell structure for a MOS-DRAM. An nMOS-FET 53 and a capacitor 50 are formed on a p-well 52. The gate 54 of the FET 53 is connected to a word line WL, the drain 56 is connected to a bit line BL, and the source 55 is connected to one electrode of the capacitor 50 whose other electrode is connected to a cell plate 51.
In the memory cell 57 of this structure, when an high level signal is given through the word line WL to the gate 54, the FET 53 conducts and the capacitor 50 is charged/discharged through the source 55, drain 56, and bit line BL, to perform a write or refresh operation/read operation.
In the memory cell 57, however, the charge stored on the capacitor 50 continuously leaks away. This leakage is caused because of subthreshold leakage through the channel of the FET 53 shown by an arrow 58 or junction leakage at the p-n junction shown by an arrow 59. When peripheral circuitry and the bit line BL are in the standby state, the junction leakage is the main cause; when peripheral circuitry and the bit line BL are in the active state, the subthreshold leakage is the main cause.
In the MOS-DRAM, refreshing (rewriting) is performed to refresh the stored contents to compensate for the loss due to the above leakage of the memory cell 57. There are two types of refresh: pause refresh that is performed when the peripheral circuitry and the bit line BL are in the standby state, and disturb refresh that is performed when the peripheral circuitry and the bit line BL are in the active state. As the leakage increases, the refresh cycle must be made shorter to perform refresh with higher frequency.
When the substrate potential (p-well potential) of the FET 53, which is usually a negative potential, is reduced in magnitude to reduce the junction leakage, the magnitude of the threshold voltage for the FET 53 decreases and the junction leakage is reduced. This, however, causes the problem that the subthreshold leakage increases.
In "MT(Multi-Threshold)-CMOS: 1 V High-Speed CMOS Digital Circuit Technology, 1994, The Institute of Electronics, Information and Communication Engineers Spring Convention, C-627,5-195" and "1 V High-Speed Digital Circuit Technology with 0.5 .mu.m Multi-Threshold(MT) CMOS, (Proc. IEEE ASIC Conf., 1993, pp 186-189)" there is disclosed a CMOS circuit constructed with pMOS and nMOS FETs having two kinds of threshold voltages, a high threshold voltage and a low threshold voltage. The CMOS circuit using the MT-MOS technology is intended to reduce the subthreshold current that flows during standby state and to increase operating speeds in active state. The circuit construction is as follows. The logic circuit is constructed with low-threshold voltage (0.3 to 0.4 V) FETs. The power supply line and secondary power supply line are connected via a high-threshold voltage (0.7 V) FET that is used to shut off the leak path. Further, the ground line and secondary ground line are connected via another high-threshold voltage (0.7 V) FET. The logic circuit is connected between the secondary power supply line and the secondary ground line.
FIG. 3 is a circuit diagram showing a CMOS circuit using the MT-MOS technology in which the logic circuit is composed of an inverter array. The gates of a pMOS-FET Q51 and nMOS-FET Q52 in an inverter I.sub.5 are connected to form an input node IN, while the node between the drains of the pMOS-FET Q51 and nMOS-FET Q52 is connected to the node between the gates of a pMOS-FET Q53 and nMOS-FET Q54 in an inverter I.sub.6. Likewise, the node between the drains of the pMOS-FET Q53 and nMOS-FET Q54 is connected to the node between the gates of a pMOS-FET Q55 and nMOS-FET Q56 in an inverter I.sub.7, while the node between the drains of the pMOS-FET Q55 and nMOS-FET Q56 is connected to the node between the gates of a pMOS-FET Q57 and nMOS-FET Q58 in an inverter I.sub.8. The drains of the pMOS-FET Q57 and nMOS-FET Q58 are connected to form an output node OUT.
The sources of the pMOS-FETs Q51, Q53, Q55, and Q57 are connected to a secondary power supply line V.sub.CC1, while the sources of the nMOS-FETs Q52, Q54, Q56, and Q58 are connected to a secondary ground line V.sub.SS1. The secondary power supply line V.sub.CC1 is connected to a power supply line V.sub.CC (power source potential: V.sub.CC) via a pMOS-FET Q59 whose gate is supplied with an inverted clock signal #.phi.. The secondary ground line V.sub.SS1 is connected to a ground line V.sub.SS (ground potential: V.sub.SS) via an nMOS-FET Q60 whose gate is supplied with a clock signal .phi.. The threshold voltage of the FETs Q59 and Q60 is larger than that of the FETs Q51, Q52, Q53, Q54, Q55, Q56, Q57, and Q58 that form the inverters I.sub.5, I.sub.6, I.sub.7, and I.sub.8.
For the inverter array using the MT-MOS-FETs, the FETs Q59 and Q60 are caused to conduct in active state. As a result, the power source potential V.sub.CC is given to the sources of the pMOS-FETs Q51, Q53, Q55, and Q57 via the secondary power supply line V.sub.CC1, while the sources of the nMOS-FET Q52, Q54, Q56, and Q58 are supplied with the ground potential V.sub.SS via the secondary ground line V.sub.SS1.
In standby state, on the other hand, the FETs Q59 and Q60 are nonconducting. This disconnects the secondary power supply line V.sub.CC1 from the power source potential V.sub.CC and the secondary ground line V.sub.SS1 from the ground potential V.sub.SS. As a result, the current path between the power supply and ground is cut off, and therefore, the subthreshold current is reduced.
The low threshold voltage of the FETs Q51, Q52, Q53, Q54, Q55, Q56, Q57, and Q58 that form the inverters I.sub.5, I.sub.6, I.sub.7, and I.sub.8 allows high-speed operations during active state. However, since the subthreshold current flows through the inverter array during standby state, the potential on the secondary power supply line V.sub.CC1 may drop or the potential on the sub ground line V.sub.SS1 may rise. When this happens, when switching from standby to active state, a significant delay may occur in the switching because of such changes in the potential of the secondary power supply line V.sub.CC1 or of the secondary ground line V.sub.SS1, and in the worst case, the logic may change. Such a phenomenon is pronounced when the active period is long.
FIG. 4 is a circuit diagram showing a word driver configuration. Each word driver WD consists of a pMOS-FET Q61 and an nMOS-FET Q62 connected in series between the ground and the power supply line V.sub.PP connected to a voltage-raising power supply; a decoder signal X is inputted to the gates of the pMOS-FET Q61 and nMOS-FET Q62, and a word line WL is connected to the node between the drains of the pMOS-FET Q61 and nMOS-FET Q62. Word drivers WD of such configuration are arranged in a matrix array, n word drivers in each column and m word drivers in each row (WD.sub.11 to WD.sub.mn).
When the decoder signal X.sub.11 is inputted to the selected word driver (for example, the word driver WD.sub.11), the associated word line WL is activated.
In this configuration, however, subthreshold current flows into the word drivers in the standby state; this becomes a problem in realizing low-power dissipation circuit design.
As the countermeasure, Japanese Patent. Application Laid-Open No. 5-210976 (1993) discloses a word driver which incorporates a converting means (FET) for switching the power source potential on and off to the pMOS-FET Q61 in the word driver WD, thereby preventing the subthreshold current from flowing.
Furthermore, "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's, Symposium on VLSI Circuit Dig. of Tech. Papers, pp. 45-46" discloses a hierarchical-structured word driver configuration that is provided, between the word driver and the above-mentioned converting means, with another converting means (FETs) for switching supply of the power source potential to the pMOS-FET Q61 in the word driver WD on a column-by-column basis. FIG. 5 is a circuit diagram showing this word driver configuration. The power supply line V.sub.PP is connected via a pMOS-FET Q70 to pMOS-FETs Q71, Q72, . . . , Q7m which are connected to word driver columns B1, B2, . . . , Bm, respectively. To the gates of the FETs Q71, Q72, . . . , Q7m are supplied with column select signals K1, K2, . . . , Km each of which is set to "L" only when the corresponding word driver column, B1, B2, . . . , Bm, contains the word driver WD to be selected.
In the above configuration, when switching to the active state from the standby state in which the source voltage of the pMOS-FET Q61 is at a slightly dropped level, there is no need to raise the source voltage for the pMOS-FETs Q61 in all the word drivers WD, and it is only necessary to raise the source voltage for the word driver column containing the selected word driver. This reduces the current consumption associated with the switching.
The word driver configuration shown in FIG. 5, however, has the problem that the rising of the selected word line delays since the source voltage of the pMOS-FET Q61 need to be raised from a slightly dropped level to the power source potential when switching from the standby state to the active state.